`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:42:44 07/08/2015
// Design Name:   LatchIFID
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/LachtIFIDTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: LatchIFID
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module LachtIFIDTest;

	// Inputs
	reg [31:0] InstruccionIn;
	reg [31:0] E1AdderIn;
	reg clk;

	// Outputs
	wire [31:0] InstruccionOut;
	wire [31:0] E1AdderOut;

	// Instantiate the Unit Under Test (UUT)
	LatchIFID uut (
		.InstruccionIn(InstruccionIn), 
		.E1AdderIn(E1AdderIn), 
		.clk(clk), 
		.InstruccionOut(InstruccionOut), 
		.E1AdderOut(E1AdderOut)
	);

	initial begin
		// Initialize Inputs
		InstruccionIn = 0;
		E1AdderIn = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
      InstruccionIn = 32'h CBAE5CAB;
		#100;
		InstruccionIn = 32'h CABE5CBA;
		// Add stimulus here

	end
	
always begin
#1;	clk = ~clk;
end     
endmodule

